1. Field of the Invention
The present invention relates to a data transmission circuit for a dynamic random access memory (DRAM) in a semiconductor memory device, and in particular to the data transmission circuit suitable for a high-speed operation as well as a high scale of integration.
2. General Description of the Prior Art
As a semiconductor memory device is getting more and more integrated and enlarged in its capacity, a requirement has been raised to achieve more high-speed input/output data transmission, as well as to carry out an error-free transmission of data. To fulfill the requirement, it is well known to those skilled in the art that a prompt and correct sensing operation in bit lines for data to be transmitted, good amplification performance of a sense amplifier for amplifying a potential difference on the bit lines, and an effective layout of every memory element, should be well balanced together.
One of prior art data transmission circuits is disclosed in FIG. 1, while its operational timing diagram is shown in FIG. 2. The prior art data transmission circuit includes memory cells 9, 10, word lines 11, 12, bit lines (BL/BL) 15, 16, a sense amplifier 7 coupled to the bit lines, isolation transistors 1 to 4 for isolating of the memory cells, input/output transistors 5, 6 coupled to the bit lines, input/output lines 13, 14 coupled to the input/output transistors, and a sense amplifier 8 coupled to the input/output lines. To each control gate of the input/output transistors 5, 6 is connected a column select line (CSL).
During a read operation of data stored in a memory cell 9, the isolation transistors 1, 2, coupled to the same memory cell are all turned on, while the other isolation transistors 3, 4 are turned off. At the moment, a word line 11 of the memory cell is selected to transmit the data onto the bit line BL, and a potential difference between the bit lines BL and BL is then amplified by the sense amplifier 7. The data transmitted onto the bit lines 15, 16 are further transmitted to the input/output lines 13, 14 through each input/output transistor 5, 6 by selection of the column select line. The electric potential of the data that has gone down due to parasitic capacitance on the input/output lines, is then increased again by the input/output sense amplifier 8. The characteristic of this data transmission circuit may be that the bit lines 15, 16 and the input/output lines 13, 14 are both arranged to be coupled with each drain and source area of the input/output transistors 5, 6. Therefore, the column select line (CSL) has to be selected subsequent to enough increase of the potential difference in the bit lines, thus leading to decrease of its operation speed due to existence of a delay time, wherein as seen in FIG. 2, about one volt of enables a logic high state. The electric potential of the data transmitted onto the input/output lines has a voltage drop by each threshold voltage of the input/output transistors 5, 6. Further, when the input/output transistors are turned on, the input/output lines 13, 14 and the bit lines 15, 16 are connected to each other so as to increase the parasitic capacitance. Hence, the potential difference in each data transmitted onto the input/output lines is further decreased so that the sensing capability of the input/output sensing amplifier 8 is considerably deteriorated.
Other example of prior art data transmission circuits, trying to resolve such a drawback in the circuit of FIG. 1, is disclosed in FIG. 3, which is known from a technical paper relating to 64 Mega DRAM device of "1990 Symposium of VLSI Circuit" by a Japanese company Hitachi. This circuit includes memory cells 33, 34, isolation transistors 21 to 24, bit lines 39, 40 and sense amplifiers 32, 41 similar to those in the FIG. 1 circuit. However, one of the most important differences between FIG. 1 and FIG. 3, may be that the bit lines 39, 40 are respectively coupled to each gate of output transistors 25, 26. Thus, there are provided not only a pair of data input lines 35, 36 and a pair of data output lines 37, 38, but also a pair of input transistors 29, 31 and a pair of output transistors 25, 26, each further connected to the bit lines, or the input/output lines. The circuit further includes a pair of transmission transistors 28, 30 connecting the input lines 35, 36 to the input transistors 29, 31, and a discharge transistor 27 coupling either one end of the output lines 37, 38 to a reference potential, for example, a ground.
Referring to FIG. 3, in case of reading out data stored in a memory cell 33, the data is amplified by the sense amplifier 32 through the isolation transistor 21. At this moment, once the column select line (CSL) is selected, the discharge transistor 27 is turned on to thereby turn on the output transistors 25, 26. Thus the sense amplifier 41 is enabled to operate. Then a difference of current drive in between the output transistors 25, 26 depending on the potential difference of the data in the bit lines 39, 40 causes different data to be transmitted onto the output lines 37, 38, finally passing through the output sense amplifier 41. In the meanwhile, in case of writing data into the memory cell 33, once the data is transmitted onto the data input lines 35, 36, the input transistors 29, 31 are turned on. Then, once the column select line (CSL) is selected, the transmission transistors 28, 30 connected to the data input lines 35, 36 are also turned on, so that the data transmission is carried out by connecting the input lines with the bit lines 39, 40.
This data transmission circuit as aforementioned, has improved data transmission speed as compared to that of FIG. 1, since its bit lines 39, 40 are directly connected to each gate of the output transistor. However, during a write operation, an electric potential of data is often subject to a voltage drop by a total sum of threshold voltages in the input transistors and the transmission transistors, thereby resulting in insufficient amplification of the potential difference. Further, the respective input and output lines are necessary and too many transistors are to be employed in connection with data input/output operation, which serves as an undesirable drawback for high-scale integration of semiconductor memory devices.